A typical six-transistor memory cell used for complementary metal-oxide-semiconductor (CMOS) static random access memories (SRAMs) consists of two cross-coupled digital inverters that combine to store one bit of information, and two access transistors on both sides of the memory cell that connect the memory cell to two bitlines. Typically, the storage state of the memory cell (i.e., “logic 0” or “logic 1”) is stored at the output of one of the digital inverters while the output of the other digital inverter is the inverse or complement of this storage state. The access transistors protect the value stored in the memory cell when the memory cell is not being accessed.
FIG. 1 shows a conventional six-transistor CMOS SRAM memory cell 100. The memory cell includes a first digital inverter 110 comprising NFET N1 and PFET P1. This first digital inverter has its input at the connection between the gates of NFET N1 and PFET P1 and its output at storage node S1. The memory cell also includes a second digital inverter 120 comprising NFET N2 and PFET P2 with its input at the connection between the gates of NFET N2 and PFET P2 and with its output at storage node S2. Storage node S1 is connected to the gates of NFET N2 and PFET P2, and storage node S2 is connected to the gates of NFET N1 and PFET P1 in a cross-coupled configuration. During a READ mode operation, bitlines BL1 and BLN1 axe initially precharged to a high logic state voltage (e.g., supply voltage VDD) and then set into a high impedance state. Wordline WL1 is then activated and access transistors N3 and N4 are turned on so that the voltages on the outputs of the digital inverters can be sensed. The digital inverters act to discharge either bitline BL1 or bitline BLN1 to ground depending on the stored state of the memory cell. Thus, in a READ mode operation, the digital inverters in the memory cell drive the bitlines. The state of bitline BL1 and bitline BLN1 are subsequently determined by external logic circuitry to determine the storage state of the memory cell
To write new data into the memory cell 100, external drivers are activated to drive the bitlines BL1 and BLN1 to the intended storage values fox storage nodes S1 and S2 while the wordline WL1 is set high and the access transistors N3 and N4 are turned on. The voltage on bitline BLN1 will be the complement of the voltage on bitline BL1. Since the external drivers are much larger than the small transistors used in the SPAM memory cell, they easily override the previous state of the cross-coupled digital inverters 110, 120.
It is a goal of SRAM integrated circuit designers and manufacturers to continually reduce the area that a SRAM memory cell occupies on an integrated circuit. In this way. SRAM memory circuitry may be made to perform better and to be produced more inexpensively. Unfortunately, however, the more the size of a conventional SRAM memory cell is decreased, the greater the likelihood that the memory cell will suffer from mismatches in threshold voltages between the CMOS transistors that form the memory cell. The threshold voltage of a CMOS transistor is typically a function of dopant profile, dielectric thickness, trapped charge in the dielectric and other factors As technology scales down, these factors become increasingly more difficult to control. As a result, significant mismatches can easily occur in the threshold voltages of CMOS transistors within the same SRAM memory cell.
These threshold voltage mismatches may, in turn, cause an instability to occur in the SRAM memory cell during READ mode operations Assume, for example, that storage node S1 in memory cell 100 is at a low logic state voltage (e.g., ground) and that NFET N1 has an abnormally high threshold voltage while access transistor N3 has an abnormally low threshold voltage. As mentioned before, during a READ mode operation, bitlines BL1 and BLN1 are initially precharged to a high logic state voltage (e.g., VDD) before the wordline WL1 turns on the access transistors N3 and N4 After turning on the access transistors N3, N4, the high threshold voltage of NF ET N1 and the low threshold voltage of the access transistor N3 may cause the voltage at storage node S1 to temporarily spike when connected to bitline BL1. This voltage spike may be sufficiently high and fast to flip the stored voltage level at storage node S2 before the value stored at storage node S2 has a chance to be sensed. This causes the SRAM memory cell to lose its proper storage state and a read error to occur. Merely allowing longer read times will not correct this stability problem since the memory cell loses its proper storage state at the beginning of the READ mode sequence.
Other combinations of threshold voltage mismatches can cause similar READ mode operation failures in conventional SRAM memory cells. There is, as a result, a need for a SRAM memory cell design that overcomes these types of failures.